The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure of a flip-flop constituting a memory cell in a memory device.
The memory cell of Static RAM type comprises a pair of driver transistors, a pair of transfer gate transistors coupled to the driver transistors and digit lines and a pair of load elements coupled to a power supply line and the driver transistors. The driver transistors constitute a flip-flop circuit. When these transistors are insulated gate type field effect transistors (hereinafter referred to IGFET), a drain region of a first driver IGFET is connected to a gate electrode of a second driver IGFET so as to obtain a first node while a drain region of the second driver IGFET is connected to a gate electrode of the first driver IGFET so as to obtain a second node. This circuit is used in a state wherein, depending on whether each of the first and second driver IGFET's is an n-channel type or a p-channel type, the common source region is connected to a low-potential side or a high-potential side and the two nodes are separately connected to a power source either on a high-potential side or on a low-potential side through load elements.
There has recently been a strong demand for the provision of a large-scale, highly-integrated type of semiconductor integrated circuit by developments in minute processing techniques. In these circumstances, however, if the flip-flop structure which relies upon the conventional structure is to be miniaturized, it involves the disadvantage of losing resistance to the alteration of stored information which is caused by natural radiation and the rays radiating from unstable radioisotopes contained in package material, a so-called soft error. Specifically, soft error is the phenomenon by which the above-mentioned radiation mainly composed of .alpha. particles causes ionization in the nodes of each flip-flop, the substrate and so forth, and excessive electrical charges are thus produced to temporarily change the potential of each node, thereby causing the state of the flip-flop to be inverted. This phenomenon frequently occurs when, as a result of miniaturization, an impurity diffused layer and so forth are made small and the electrical capacitance of each node is thus reduced since the above-mentioned electrical charges are recombined and each node potential thus easily fluctuates. In order to solve this disadvantage, it is preferable to prevent any decrease in the electrical capacitance of each node while satisfying the need for miniaturization. To this end, what might first be considered is to enhance the impurity concentration in the semiconductor substrate so as to increase the junction capacitance of the drain region of the driver transistor which forms each node. However, in this case, the transfer gate IGFET's are also formed in the same semiconductor substrate of high impurity concentration, and therefore, the electrical capacitance of source or drain region of the transfer gate IGFET and that of the digit line coupled to a plurality of the transfer gate IGFET's are enhanced. Consequently, the switching or operation speed for reading and writing is delayed. Another method which might be considered is to locate close together the diffused drain regions of the pair of the driver IGFET's constituting the nodes of the IGFET's which form flip-flops, so that their capacitance can be mutually increased. However, in a memory device having flip-flops which are arranged at a high density, a pattern providing interconnection, for example, an aluminum pattern, is normally formed over the structure with an insulating layer film interposed therebetween by a deposition process, reducing the threshold voltage of a parasitic transistor formed between the impurity diffused drain regions of the driver IGFET's as source and drain. Therefore, it is impossible to allow to come close enough to the drain regions to affect an increase in the electrical capacitance of each node.